A common circuit configuration for a switching regulated power supply utilizes an output power transistor in a common base configuration, with the regulated output voltage being derived at the emitter of the power transistor. Typically, the base of the transistor is driven by a transformer, to which the output of a pulse width modulator is capacitively coupled. The pulse width control input of the pulse width modulator is then coupled to the regulated output of the power supply so as to compensate for variations in the regulated output voltage.
Capacitive coupling between the pulse width modulator and the drive transformer makes it difficult to switch the power transistor rapidly. Under normal operation, the power transistor is periodically switched in and out of saturation. Owing to the capacitive coupling of the pulse width modulator, the negative swing of the signal applied to the drive transformer is very small, when the output signal of the pulse width modulator is at a low duty cycle. As a result, very little reverse drive is available at the base of the power transistor to drive it out of saturation, and the power transistor turns off very sluggishly. This results in excessive power consumption and also presents a substantial limitation on the degree of regulation provided by the power supply.
Broadly, it is an object of the present invention to overcome the disadvantages inherent in prior art switching regulators utilizing a capacitively coupled pulse width modulator. It is specifically contemplated that the invention provide substantial reverse drive to the power transistor so as to minimize the switching delays resulting from the charge storage time associated with saturation of the transistor.
It is also an object of the present invention to provide circuit means for improving the switching speed of the power transistor, which circuit means is readily retrofitted into existing switching regulated power supplies, is convenient and reliable in use, yet relatively simple and inexpensive construction.
In accordance with an illustrative embodiment demonstrating objects and features of the present invention, an active speed-up circuit is provided across a buffer amplifier which is in series circuit between the pulse width modulator and coupling capacitor. The speed up circuit includes a time delay circuit which is activated when the output of the amplifier goes low. The delay circuit is coupled to actuate a clamp circuit at a predetermined interval after actuation. The clamp circuit is connected to the input of the amplifier and, upon actuation, pulls up the voltage at the input of the amplifier so that it is at a level intermediate the extreme values of the pulse width modulator output signal.
In a preferred embodiment, the timer is an series RC charging circuit and the clamp is a transistor with its base connected to the junction between the capacitor and the resistor. The collector of the transistor is coupled to the input of the amplifier and its emitter is connected to a voltage source through a zener diode.